1. Field of the Invention
The present invention relates generally to a semiconductor memory device, and more particularly, to a semiconductor memory device having a transistor/capacitor cell formed on a protrusion or island to increase integration density.
2. Description of the Prior Art
FIG. 1 is a block diagram showing exemplary structure of a general RAM. Referring to FIG. 1, a memory cell array 101 is formed by a plurality of word lines and a plurality of bit lines which intersect with each other to be provided with memory cells in respective intersections. A memory cell is selected on the basis of an intersection between a word line selected by an X-address buffer decoder 102 and a bit line selected by a Y-address buffer decoder 103. Indication for writing/reading data in/from the selected memory cell is made by a read/write control signal R/W which is supplied to an R/W control circuit 104. In data writing, input data D.sub.in is inputted in the selected memory cell through the R/W control circuit 104. In data reading, on the other hand, data stored in the selected memory cell is detected by a sense amplifier 105 and thereafter amplified, to be outputted to the exterior through a data output buffer 106 as output data D.sub.out.
FIG. 2 shows an equivalent circuit diagram of a dynamic type memory cell, for illustrating write/read operation for the memory cell.
Referring to FIG. 2, the dynamic memory cell is formed by a field-effect transistor 108 and a capacitor 109. The gate electrode of the field-effect transistor 108 is connected to a word line 110 and a source/drain electrode, which is connected with the capacitor 109, is connected to a bit line 107 respectively. In data writing, the field-effect transistor 108 conducts by application of a prescribed potential to the word line 110, whereby charges applied to the bit line 107 are stored in the capacitor 109. In data reading, on the other hand, the field-effect transistor 108 conducts by application of a prescribed potential to the word line 110, whereby the charges stored in the capacitor 109 are drawn out through the bit line 107.
FIG. 3 illustrates plane layout of a memory part of a dynamic MOSRAM (random access memory) being in folded bitline structure, and FIG. 4 is a sectional view taken along the line IV--IV in FIG. 4.
The structure of the dynamic MOSRAM is now described with reference to these figures.
The RAM is provided with pairs of MOS transistors and capacitors formed in active regions 112, which are isolated from adjacent elements by isolation oxide films 2 formed on prescribed positions of the major surface of a semiconductor substrate 1. Each MOS transistor is formed by impurity layers 5 and 11 formed on the major surface of the semiconductor substrate 1 to serve as source or drain regions and a word line 4 for serving as a gate electrode formed through a gate dielectric film 7 on a region between the impurity layers 5 and 11. Each capacitor is formed by an impurity layer 5b provided in a region between the impurity layer 5 and the isolation oxide film 2 and a cell plate 3 provided on the impurity layer 5b to also cover the isolation oxide film 2 through a capacitor dielectric film 6. An interlayer isolation film 9 is formed by an oxide film to cover the transistor and the capacitor, and a bit line 8 formed on the interlayer isolation film 9 is connected to the impurity layer 11 through a contact 111 in a contact hole 113 which is provided in the interlayer isolation film 9. Further, the bit line 8 is covered and protected by a surface protective coat 10 which is formed by a nitride film.
In the RAM of such structure, a prescribed potential is applied to a selected word line 4 to allow conduction of the region between the impurity layers 5 and 11 under the same, thereby to perform read/write operation.
In the conventional semiconductor memory device, MOS structural members forming each semiconductor device such as the aforementioned MOS transistor and the capacitor for storing information charges are arranged on the plane of the semiconductor substrate 1. Thus, the area occupied by such members has reached the limit in the current 1-Mb semiconductor memory device of MOS random access type, which is directed to increase in integration density. Thus, it has been very difficult to further increase integration density.
"A High Density 4M DRAM Process Using Folded Bitline Adaptive Side-Wall Isolated Capacitor (FASIC) Cell" by M. Nagatomo et al., 1986 IEDM, pp. 144-147 discloses technique of forming capacitors of respective elements by providing impurity regions in sidewalls of trenches longitudinally formed around element regions.
However, the disclosure in the above described document fails to achieve high integration density and high reliability according to the present invention because a transistor part is formed in a plane part or a method for preventing interference between a capacitor formed on the sidewall of a trench and an adjacent cell is not clearly shown.